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CY7C455 CY7C456 CY7C457
512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags
Features
* High-speed, low-power, first-in first-out (FIFO) memories * 512 x 18 (CY7C455) * 1,024 x 18 (CY7C456) * 2,048 x 18 (CY7C457) * 0.65 micron CMOS for optimum speed/power * High-speed 83-MHz operation (12 ns read/write cycle time) * Low power -- ICC=90 mA * Fully asynchronous and simultaneous read and write operation * Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags * TTL compatible * Retransmit function * Parity generation/checking * Output Enable (OE) pins * Independent read and write enable pins * Center power and ground pins for reduced noise * Supports free-running 50% duty cycle clock inputs * Width Expansion Capability * Depth Expansion Capability * 52-pin PLCC and 52-pin PQFP
Functional Description
The CY7C455, CY7C456, and CY7C457 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide. The CY7C455 has a 512-word memory array, the CY7C456 has a 1,024-word memory array, and the CY7C457 has a 2,048-word memory array. The CY7C455, CY7C456, and CY7C457 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Empty flags and generation/checking of parity. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW).
Logic Block Diagram
D0 -
17
Pin Configurations
PLCC Top View
VCC VCC(N) D3 D4 D5 D6 D7 D8 VSS D9 D10 D11 D12
INPUT REGISTER
CKW
ENW
PARITY WRITE CONTROL
FLAG/PARITY PROGRAM REGISTER
7 6 5 4 3 2 1 52 51 50 49 48 47 8 9 10 XI 11 HF ENW 12 E/F CKW 13 PAFE/XO HF 14 E/F 15 XO/PAFE 16 Q0 17 Q1 18 Q2 19 Q3 20 Q4 Q5 Q6 Q7 Q8 /PG1/PE1 VSS D2 D1 D0 46 45 44 43 42 41 40 39 38 37 36 35 34 29 30 31 32 33 Q11 Q12 Q13 Q14 c455-2 D13 D14 D15 D16 D17 FL/RT MR CKR ENR OE Q17/PG2/PE2 Q16 Q15
FLAG LOGIC RAM ARRAY 512 x 18 1024 x 18 2048 x 18
7C455 7C456 7C457
WRITE POINTER MR FL/RT XI RESET LOGIC
READ POINTER
21 22 23 24 25 26 27 28
EXPANSION LOGIC
THREE-STATE OUTPUT REGISTER OE Q0 - 7 , Q8 /PG1/PE1 Q9- 16 , Q17/PG2/PE2
READ CONTROL
RETRANSMIT LOGIC
CKR
ENR
c455-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 October 1992 - Revised January 3, 1997
VSS(N) Q9 Q10
CY7C455 CY7C456 CY7C457
Pin Configurations (continued)
PQFP Top View
D4 D5 D6 D7 D8 VSS VCC VCC(N) D9 D10 D11 D12 D3
Functional Description (continued)
In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (ENR) and the write enable (ENW) must both be HIGH during the retransmit, and then ENR is used to access the data.When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a free-running read clock (CKR) and a read enable pin (ENR). In addition, the CY7C455, CY7C456, and CY7C457 have an output enable pin (OE). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 83.3 MHz are achievable in the standalone configuration, and up to 83.3 MHz is achievable when FIFOs are cascaded for depth expansion. Depth expansion is possible using the cascade input (XI), cascade output (XO), and First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device. The FL pin of the first device is tied to VSS. The CY7C455, CY7C456, and CY7C457 provide three status pins. These pins are decoded to determine one of six states: Empty, Almost Empty, Less than or Equal to Half Full, Greater than Half Full, Almost Full, and Full (see Table 1). The Almost Empty/Full flag (PAFE) shares the XO pin on the CY7C455, CY7C456, and CY7C457. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (XO) information that is used to signal the next FIFO when it will be activated. The flags are synchronous, i.e., they change state relative to either the read clock (CKR) or the write clock (CKW). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the CKR. The flags denoting Half Full, Almost Full, and Full states are updated exclusively by CKW. The synchronous flag architecture guarantees that the flags maintain their status for some minimum time. This time is typically equal to approximately one cycle time. The CY7C455/6/7 uses center power and ground for reduced noise. All configurations are fabricated using an advanced 0.65u CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.
52 51 50 49 48 47 46 45 44 43 42 41 40 D2 D1 D0 XI ENW CKW HF E/F XO/PAFE Q0 Q1 Q2 Q3 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 7C455 33 7C456 7C457 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26
D13 D14 D15 D16 D17 FL/RT MR CKR ENR OE Q17/PG2/PE2 Q16 Q15
c455-3 Q4 Q5 Q6 Q7 Q8/PG1/PE1 VSS VSS(N) Q9 Q10 Q11 Q12 Q13 Q14
2
CY7C455 CY7C456 CY7C457
Selection Guide
7C455/6/7-12 Maximum Frequency (MHz) Maximum Cascadable Frequency Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Clock HIGH Time (ns) Minimum Clock LOW Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Maximum Current (mA) Commercial Industrial 83.3 83.3 9 12 5 5 4 0 9 160 180 7C455/6/7-14 71.4 71.4 10 14 6.5 6.5 5 0 10 160 180 7C455/6/7-20 50 50 15 20 9 9 6 0 15 140 160 7C455/6/7-30 33.3 33.3 20 30 12 12 7 0 20 120 140
Selection Guide (continued) CY7C455 Density OE, Depth Cascadable Package 512 x 18 Yes 52-Pin PLCC/PQFP CY7C456 1,024 x 18 Yes 52-Pin PLCC/PQFP CY7C457 2,048 x 18 Yes 52-Pin PLCC/PQFP
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................-65C to +150C Ambient Temperature with Power Applied ............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial
[1]
Ambient Temperature 0C to +70C -40C to +85C
VCC 5V 10% 5V 10%
Note: 1. TA is the "instant on" case temperature.
3
CY7C455 CY7C456 CY7C457
Pin Definitions
Signal Name D0 - 17 I/O I Description Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D 0 - 17) into the FIFO's memory. If MR is asserted at the rising edge of CKW, data is written into the FIFO's programming register. D 8 , 17 are ignored if the device is configured for parity generation. Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q 0 - 7 , Q 9 - 16) out of the FIFO's memory. If MR is active at the rising edge of CKR, data is read from the programming register. Function varies according to mode: Parity disabled - same function as Q0 - 7 and Q 9 - 16 Parity enabled, generation - parity generation bit (PGx) Parity enabled, check - Parity Error Flag (PE x) Enable Write: Enables the CKW input (for both non-program and program modes). Enable Read: Enables the CKR input (for both non-program and program modes). Write Clock: The rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and Full flag states. When MR is asserted, CKW writes data into the program register. Read Clock: The rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and Almost Empty flag states. When MR is asserted, CKR reads data out of the program register. Half Full Flag: Synchronized to CKW. Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW. Dual-Mode Pin: Not Cascaded - programmable Almost Full is synchronized to CKW; Programmable Almost Empty is synchronized to CKR. Cascaded - expansion out signal, connected to XI of next device. Expansion-In Pin: Not Cascaded - XI is tied to VSS. Cascaded - expansion Input, connected to XO of previous device. First Load/Retransmit Pin: Cascaded - the first device in the daisy chain will have FL tied to VSS; all other devices will have FL tied to VCC (Figure 1). Not Cascaded - tied to VCC. Retransmit function is also available in standalone mode by strobing RT. Master Reset: Resets device to empty condition. Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at 16 or less locations from Full/Empty. Programming Mode: Data present on D0 - 9,10, or 11 and D15-17 is written into the programmable register on the rising edge of CKW. Program register contents appear on Q 0 - 9,10, or 11 and Q15-17 after the rising edge of CKR. Output Enable for Q0 - 7, Q 9 - 16 , Q 8/PG1/PE1 and Q 17 /PG2/PE2 pins.
Q0 - 7 Q 9 - 16 Q8/PG1/PE1 Q 17/PG2/PE2
O
O
ENW ENR CKW CKR HF E/F PAFE/XO
I I I I O O O
XI
I
FL/RT
I
MR
I
OE
I
4
CY7C455 CY7C456 CY7C457
Electrical Characteristics Over the Operating Range
7C455/6/7- 12 Parameter VOH VOL VIH[2] VIL IIX IOS[3] IOZL IOZH ICC1[4] ICC2[5] ISB[6]
[2]
7C455/6/7- 7C455/6/7- 7C455/6/7- 14 20 30 Min. 2.4 Max Min. 2.4 0.4 2.2 -0.5 -10 -90 VCC 0.8 +10 2.2 -0.5 -10 -90 +10 160 180 90 100 40 40 -10 +10 140 160 90 100 40 40 0.4 VCC 0.8 +10 2.2 -0.5 -10 -90 -10 +10 120 140 90 100 40 40 Max Min. 2.4 0.4 VCC 0.8 +10 Max Unit V V V V A mA A mA mA mA mA mA mA
Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Short Circuit Current Output OFF, High Z Current Operating Current Operating Current Standby Current
Test Conditions VCC = Min., I OH = -2.0 mA VCC = Min., I OL = 8.0 mA
Min. 2.4
Max
0.4 2.2 -0.5 VCC 0.8 +10
VCC = Max. VCC = Max., VOUT = GND OE > VIH, V SS < VO < VCC VCC = Max., IOUT = 0 mA VCC = Max., IOUT = 0 mA VCC = Max., IOUT = 0 mA Com'l Ind Com'l Ind Com'l Ind
-10 -90 -10
+10 160 180 90 100 40 40
-10
Capacitance[7]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, V CC = 5.0V Max. 10 12 Unit pF pF
AC Test Loads and Waveforms[8, 9, 10, 11, 12]
R1 500 5V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT 200 OUTPUT R2 333 3.0V GND 3 ns
ALL INPUT PULSES
90% 10% 90% 10% 3 ns
c455-5
c455-4
2V
Notes: 2. The VIH and VIL specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or V SS. 3. Test no more than one output at a time for not more than one second. 4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (fMAX), while data inputs switch at f MAX /2. Outputs are unloaded. 5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs are unloaded. 6. All input signals are connected to VCC. All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX). 7. Tested initially and after any design or process changes that may affect these parameters. 8. CL = 30 pF for all AC parameters except for t OHZ . 9. CL = 5 pF for t OHZ. 10. All AC measurements are referenced to 1.5V except tOE, t OLZ , and t OHZ . 11. tOE and tOLZ are measured at 100 mV from the steady state. 12. tOHZ is measured at +500 mV from VOL and - 500 mV from VOH.
5
CY7C455 CY7C456 CY7C457
Switching Characteristics Over the Operating Range[13]
7C455/6/7- 7C455/6/7- 7C455/6/7- 12 14 20 Parameter tCKW tCKR tCKH tCKL tA tOH tFH tSD tHD tSEN tHEN tOE tOLZ tPG tPE tFD tSKEW1 tSKEW2 tPMR tSCMR tOHMR tMRR tMRF tAMR tSMRP tHMRP tFTP tAP tOHP tPRT tRTR
[15] [16] [7, 14] [7, 14]
7C455/6/7- 30 Min. Max. 30 30 12 12 Unit ns ns ns ns 20 0 0 7 0 7 0 ns ns ns ns ns ns ns 20 0 20 20 20 20 0 30 30 0 0 30 ns ns ns ns ns ns ns ns ns ns ns ns 30 30 30 20 30 ns ns ns ns ns 30 0 30 30 ns ns ns ns
Description Write Clock Cycle Read Clock Cycle Clock HIGH Clock LOW Data Access Time Previous Output Data Hold After Read HIGH Previous Flag Hold After Read/Write HIGH Data Set-Up Data Hold Enable Set-Up Enable Hold OE LOW to Output Data Valid OE LOW to Output Data in Low Z OE HIGH to Output Data in High Z Read HIGH to Parity Generation Read HIGH to Parity Error Flag Flag Delay Opposite Clock After Clock Opposite Clock Before Clock Master Reset Pulse Width (MR LOW) Last Valid Clock LOW Set-Up to MR LOW Data Hold From MR LOW Master Reset Recovery (MR HIGH Set-Up to First Enabled Write/Read) MR HIGH to Flags Valid MR HIGH to Data Outputs LOW Program Mode--MR LOW Set-Up Program Mode--MR LOW Hold Program Mode--Write HIGH to Read HIGH Program Mode--Data Access Time Program Mode--Data Hold Time from MR HIGH Retransmit Pulse Width Retransmit Recovery Time
Min. Max. Min. Max. Min. Max. 12 12 5 5 9 0 0 4 0 4 0 9 0 9 9 9 9 0 12 14 0 0 12 12 12 12 9 12 12 0 12 12 0 14 14 14 10 14 14 0 20 20 0 14 14 0 0 14 14 14 20 15 20 20 0 10 10 10 10 0 20 20 0 0 20 20 20 0 0 5 0 5 0 10 0 15 15 15 15 14 14 6.5 6.5 10 0 0 6 0 6 0 15 20 20 9 9 15
tOHZ
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms and capacitance as in notes 8 and 9, unless otherwise specified. 14. At any given temperature and voltage condition, tOLZ is greater than t OHZ for any given device. 15. t SKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than t SKEW1 after the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags. 16. t SKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than t SKEW2 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. See Note 15 for definition of clock and opposite clock.
6
CY7C455 CY7C456 CY7C457
Switching Waveforms
Write Clock Timing Diagram
CKW tSD D0 - 17
VALID DATA IN
tCKW tCKH
ENABLED WRITE
tCKL
DISABLED WRITE
tHD
tSEN ENW tFH E/F,PAFE,HF
tHEN
tSEN
tHEN
tFD
tFH
tFD
c455-6
Read Clock Timing Diagram
tCKH CKR
tCKR
tCKL
DISABLED READ
ENABLED READ
tOH Q0 - 17
PREVIOUS WORD
tA
NEW WORD
tSEN ENR tFH E/F,PAFE
tHEN
tSEN
tHEN
tFD
tFH
[17, 18, 19, 20]
tFD
c455-7
MasterReset (Default with Free-RunningClocks) Timing Diagram
tPMR MR tSCMR CKW
tMRR
FIRST WRITE
ENW tSCMR CKR ENR tOHMR Q0 - 17
VALID DATA
tMRR
tAMR
ALL DATA OUTPUTS LOW
tMRF E/F,PAFE tMRF HF
c455-8
Notes: 17. To only perform reset (no programming), the following criteria must be met: ENW or CKW must be inactive while MR is LOW. 18. To only perform reset (no programming), the following criteria must be met: ENR or CKR must be inactive while MR is LOW. 19. All data outputs (Q0 - 17 ) go LOW as a result of the rising edge of MR after tAMR. 20. In this example, Q0 - 17 will remain valid until t OHMR if either the first read shown did not occur or if the read occurred soon enough such that the valid data was caused by it.
7
CY7C455 CY7C456 CY7C457
Switching Waveforms (continued)
Master Reset (Programming Mode) Timing Diagram
tSMRP MR tSCMR CKW ENW
LOW LAST VALID WRITE
[19, 20]
tHMRP
tCKH
PGM WRITE
tMRR
FIRST WRITE SECOND WRITE
tFTP tSD tHD
PGM WORD WORD 1 WORD 2
D0 - 17
LAST WORD
tSCMR CKR ENR
LAST VALID READ LOW
tSMRP
PGM READ
tHMRP
tCKH tAP tOHP
PGM WORD
tOHMR Q0 - 17
VALID DATA
tAMR
ALL DATA OUTPUTS L OW c455-9
Master Reset (Programming Mode with Free-Running Clocks) Timing Diagram
tSMRP MR tSCMR CKW
LAST VALID WRITE
[19, 20]
tHMRP tCKW tCKH
PGM WRITE
tCKL
tMRR
FIRST WRITE SECOND WRITE
tSEN ENW
tHEN
tFTP D0 - 17
LAST WORD PGM WORD WORD 1 WORD 2
tCKR tSCMR CKR
LAST VALID READ
tSMRP
PGM READ
tHMRP
tMRR
tCKH tSEN tHEN
tCKL
ENR tOHMR Q0 - 17
VALID DATA
tAP
tOHP
PGM WORD
tAMR
ALL DATA OUTPUTS L OW c455-10
8
CY7C455 CY7C456 CY7C457
Switching Waveforms (continued)
Read to Empty Timing Diagram
COUNT 3 2
[21, 24, 25]
1
0
1
1 (NO CHANGE) LATENT CYCLE
0
CKR ENR
R1 ENABLED READ
R2 ENABLED READ
R3 ENABLED READ
R4 FLAG UPDATE READ
R5 ENABLED READ
tSKEW1 CKW ENW E/F
LOW
tSKEW2
W1 ENABLED WRITE
tFD
tFD
tFD
c455-12
Read to Empty Timing Diagram with Free-RunningClocks
COUNT 1 0 R1 ENABLED READ R2 IGNORED READ 1
[21, 22, 23, 24]
LATENT CYCLE
0 R5 ENABLED READ R6 IGNORED READ
CKR
R3 IGNORED READ
tSKEW2 ENR tSKEW1 CKW
W1 W2
R4 FLAG UPDATE READ
tSKEW2
W3 ENABLED WRITE W4 W5 W6
ENW
HF
HIGH
tFD E/F PAFE
LOW
tFD
tFD
c455-11
Notes: 21. "Count" is the number of words in the FIFO. 22. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full). 23. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs less than tSKEW2 before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than tSKEW2 before R4, R4 includes W3 in the flag update. 24. CKR is clock and CKW is opposite clock. 25. R3 updates the flag to the Empty state by asserting E/F. Because W1 occurs greater than t SKEW1 after R3, R3 does not recognize W1 when updating flag status. But because W1 occurs t SKEW2 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty state. It is important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count or the FIFO's data outputs.
9
CY7C455 CY7C456 CY7C457
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks
COUNT 17 16 R1 ENABLED READ 17 R2 18 R3
[21, 24, 26]
17 R4 ENABLED READ 16 R5 ENABLED READ 15 R6 ENABLED READ
CKR
ENR tSKEW1 CKW
W1
W2 ENABLED WRITE
tSKEW2
W3 ENABLED WRITE
W4
W5 W1
W6
ENW
HF
HIGH
E/F
HIGH
tFD PAFE
tFD
tFD
c455-14
Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks
18 (no change) COUNT 17 16 17 18 FLAG UPDATE CYCLE 17 16
[21, 24, 26, 27, 28]
15
CKR
R1 ENABLED READ
R2
R3
R4 FLAG UPDATE READ
R5 ENABLED READ
R6 ENABLED READ
R7 ENABLED READ
ENR tSKEW1 CKW
W1
W2 ENABLED WRITE
tSKEW2
W3 ENABLED WRITE
W4
W5
W6
W7
ENW
HF
HIGH
E/F
HIGH
tFD PAFE
tFD
tFD
c455-13
Notes: 26. The FIFO in this example is assumed to be programmed to its default flag values. Almost Empty is 16 words from Empty; Almost Full is 16 locations from Full. 27. R4 only updates the flag status. It does not affect the count because ENR is HIGH. 28. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 A18; two enabled writes: W2, W3) before a read (R4) can update flags to the Less Than Half Full state.
10
CY7C455 CY7C456 CY7C457
Switching Waveforms (continued)
Write to Half Full Timing Diagram with Free-Running Clocks
COUNT 1024 [512] [256] 1025 [513] [257] W1 ENABLED WRITE 1024 [512] [256] W2 1023 [511] [255] W3
[21, 29, 30, 31]
1024 [512] [256] W4 ENABLED WRITE 1025 [513] [257] W5 ENABLED WRITE 1026 [514] [258] W6 ENABLED WRITE
CKW
ENW tSKEW1 CKR
R1
R2 ENABLED READ
tSKEW2
R3 ENABLED READ
R4
R5
R6
ENR tFD HF tFD tFD
E/F PAFE
HIGH
HIGH
c455-15
Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks
1024 COUNT [512] [256] 1025 [513] [257] W1 ENABLED WRITE 1024 [512] [256] W2 1023 [511] [255] W3 1023 [511] [255] (no change) FLAG UPDATE CYCLE 1024 [512] [256] W5 ENABLED WRITE
[21, 29, 30, 31, 32, 33]
1025 [513] [257] W6 ENABLED WRITE
1026 [514] [258] W7 ENABLED WRITE
CKW
W4 FLAG UPDATE WRITE
ENW tSKEW1 CKR
R1
R2 ENABLED READ
tSKEW2
R3 ENABLED READ
R4
R5
R6
R7
ENR tFD HF tFD tFD
E/F PAFE
HIGH
HIGH
c455-16
Notes: 29. CKW is clock and CKR is opposite clock. 30. Count = 1,025 indicates Half Full for the CY7C446 and CY7C456. Count = 513 indicates Half Full for the CY7C447 and CY7C457. Count = 257 indicates Half Full for the CY7C448 and CY7C458. 31. When the FIFO contains 1,024 [512] [256] words, the rising edge of the next enabled write causes the HF to be true (LOW). 32. The HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH. 33. When making the transition from Half Full to Less Than Half Full, the count must decrease by two (i.e., 1,025 A1,023; two enabled reads: R2 and R3) before a write (W4) can update flags to less than Half Full.
11
CY7C455 CY7C456 CY7C457
Switching Waveforms (continued)
Write to Almost Full TimingDiagram
COUNT 2030 [1016] [494] 2031 [1017] [495] 2032 [1018] [496]
[21, 26, 29, 34, 35]
2031 [1017] [495] 2030 [1016] [494] 2031 [1017] [495] 2030 [1016] [494] W3 ENABLED WRITE FLAG UPDATE 2032 [496] 2031 [1017] [495] W4 ENABLED WRITE 2033 [497] 2032 [1018] [496] W5 ENABLED WRITE
CKW
W1 ENABLED WRITE
W2 ENABLED WRITE
ENW
LOW
tSKEW1 CKR ENR
LOW R1 ENABLED READ R2 ENABLED READ
tSKEW2
tFD PAFE HF E/F
LOW
tFD
tFD
tFD
HIGH c455-18
Write to Almost Full Timing Diagram with Free-RunningClocks
COUNT 2031 [1017] [495] 2032 [1018] [496] W1 ENABLED WRITE 2031 [1017] [495] W2 2030 [1016] [494] W3
[21, 26, 29]
2031 [1017] [495] W4 ENABLED WRITE 2032 [1018] [496] W5 ENABLED WRITE 2033 [1019] [497] W6 ENABLED WRITE
CKW
ENW tSKEW1 CKR
R1 R2 ENABLED READ
tSKEW2
R3 ENABLED READ R4 R5 R6
ENR HF
LOW
E/F
HIGH
tFD PAFE
tFD
tFD
c455-17
Notes: 34. W2 updates the flag to the Almost Full state by asserting PAFE. Because R1 occurs greater than t SKEW1 after W2, W2 does not recognize R1 when updating flag status. W3 includes R2 in the flag update because R2 occurs greater than t SKEW2 before W3. Note that W3 does not have to be enabled to update flags. 35. The dashed lines show W3 as a flag update write rather than an enabled write because ENW is HIGH.
12
CY7C455 CY7C456 CY7C457
Switching Waveforms (continued)
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks
2030 [1016] [494] (no change) 2031 COUNT [1017] [495] 2032 [1018] [496] W1 ENABLED WRITE 2031 [1017] [495] W2 2030 [1016] [494] W3 FLAG UPDATE CYCLE 2031 [1017] [495] W5 ENABLED WRITE 2032 [1018] [496] W6 ENABLED WRITE 2033 [1019] [497] W7 ENABLED WRITE
[21, 26, 29]
CKW
W4 FLAG UPDATE WRITE
ENW tSKEW1 CKR
R1 R2 ENABLED READ
tSKEW2
R3 ENABLED READ R4 R5 R6 R7
ENR HF E/F
LOW
HIGH
tFD PAFE
tFD
tFD
c455-19
Write to Full Flag Timing Diagram with Free-Running Clocks
COUNT 2047 [1023] [511] 2048 [1024] [512] W1 ENABLED WRITE 2048 [1024] [512] W2 IGNORED WRITE 2047 [1023] [511] W3 IGNORED WRITE
[21, 29, 36]
LATENT CYCLE 2048 [1024] [512] W5 ENABLED WRITE 2048 [1024] [512] W6 IGNORED WRITE
CKW
tSKEW2 ENW tSKEW1 CKR
R1 R2
W4 FLAG UPDATE WRITE
tSKEW2
R3 ENABLED READ R4 R5 R6
ENR HF
LOW
tFD E/F PAFE
LOW
tFD
tFD
c455-20
Note: 36. W2 is ignored because the FIFO is full (count = 2,048 [1,024] [512]). It is important to note that W3 is also ignored because R3, the first enabled read after full, occurs less than tSKEW2 before W3. Therefore, the FIFO still appears full when W3 occurs. Because R3 occurs greater than tSKEW2 before W4, W4 includes R3 in the flag update.
13
CY7C455 CY7C456 CY7C457
Switching Waveforms (continued)
Even Parity Generation Timing Diagram
CKR
[37, 38]
ENABLED READ
DISABLED READ
tPG PE1, (PE2) Q0- 7 (Q9 - 16) ENR
c455-21
PREVIOUS WORD: EVEN NUMBER OF 1s
NEW WORD: ODD NUMBER OF 1s
Even Parity GenerationTiming Diagram
CKR PE1, (PE2)
[37, 39]
ENABLED READ
DISABLED READ
tPG
Q0- 7 (Q9 - 16) ENR
PREVIOUS WORD: ODD NUMBER OF 1s
NEW WORD: EVEN NUMBER OF 1s
c455-22
Notes: 37. In this example, the FIFO is assumed to be programmed to generate even parity. The Q0-7 word is shown. The example is similar for the Q9-16 word. 38. If Q0-7 "new word" also has an even number of 1s, then PG1 stays LOW. 39. If Q0-7 "new word" also has odd number of 1s, then PG1 stays HIGH.
14
CY7C455 CY7C456 CY7C457
Switching Waveforms (continued)
Even Par ity Checking
CKW
WRITE M WRITE M+1 WRITE M+2
[40]
ENW
D0- 7 EVEN NUMBER
OF 1" s
WORD M:
WORD M+ 1: ODD NUMBER OF 1"s
WORD M+ 2: EVEN NUMBER OF 1" s
CKR
READ M READ M+1 READ M+2
ENR tPE F1 PE1 (PE2) Q0- 7 (Q9- 16)
8 LSBs OF WORD M-1 8 LSBs OF WORD M 8 LSBs OF WORD M+1 8 LSBs OF WORD M+2 c455-23
tPE
Output Enable Timing
CKR
[41, 42]
READ M+1
ENR
LOW
OE tOHZ Q0- 17
VALID DA TA WORD M
tOE
VALID DA TA WORD M+1
tOLZ
c455-24
Retransmit Timing
FL/RT
[43, 44]
tPRT
tRTR REN/WEN
E/F, HF, PAFE
42X5-21
Notes: 40. In this example, the FIFO is assumed to be programmed to check for even parity. The Q0-7 word is shown. 41. This example assumes that the time from the CKR rising edge to valid word M+1 > t A. The Q0-7 word is shown. 42. If ENR was HIGH around the rising edge of CKR (i.e., read disabled), the valid data at the far right would once again be word M instead of word M+1. 43. Clocks are free running in this case. 44. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
15
CY7C455 CY7C456 CY7C457
Architecture
The CY7C455/6/7 consists of an array of 512, 1024, or 2048 words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (CKR, CKW, ENR, ENW, and MR), and flags (HF, E/F, PAFE). The CY7C455/6/7 also includes the control signals OE, FL, XI, and XO for depth expansion. When free-running clocks are tied to CKW and CKR, programming can still occur during a master reset cycle with the adherence to a few additional timing parameters. The enable pins must be set-up tSEN before the rising edge of CKW or CKR. Hold times of tHEN must also be met for ENW and ENR. Data present on D0-9 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags will become active. See Table 1 for a description of the six possible FIFO states. P in Table 1 refers to the decimal equivalent of the binary number represented by D0-7, 8 or 9. Programming options for the CY7C455/6/7 are listed in Table 4. The programmable PAFE function on the CY7C455/6/7 is only valid when not cascaded. If the user elects not to program the FIFO's flags, the default is as follows: the Almost Empty condition (Almost Full condition) is activated when the FIFO contains 16 or less words (empty locations). Parity is programmed with the D15-17 bits. See Table 4 for a summary of the various parity programming options. Data present on D15-17 during a program write will determine whether the FIFO will generate or check even/odd parity for the data present on D0-7 and D9-16 thereafter. If the user elects not to program the FIFO, the parity function is disabled. Flag operation and parity are described in greater detail in subsequent sections.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the Empty condition signified by E/F and PAFE being LOW and HF being HIGH. All data outputs (Q0-17) go low at the rising edge of MR. In order for the FIFO to reset to its default state, a falling edge must occur on MR and the user must not read or write while MR is LOW (unless ENR and ENW are HIGH or unless the device is being programmed). Upon completion of the master reset cycle, all data outputs will go LOW tAMR after MR is deasserted. All flags are guaranteed to be valid tMRF after MR is taken HIGH.
FIFO Operation
When the ENW signal is active (LOW), data present on the D0-17 pins is written into the FIFO on each rising edge of the CKW signal. Similarly, when the ENR signal is active, data in the FIFO memory will be presented on the Q 0-17 outputs. New data will be presented on each rising edge of CKR while ENR is active. ENR must set up tSEN before CKR for it to be a valid read. ENW must occur tSEN before CKW for it to be a valid write. An output enable (OE) pin is provided to three-state the Q0-17 outputs when OE is asserted. When OE is enabled (low), data in the output register will be available to the Q0-17 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q 0-17 outputs even after additional reads occur.
Flag Operation
The CY7C455/6/7 provides three status pins when not cascaded. The three pins, E/F, PAFE, and HF, allow decoding of six FIFO states (Table 1). PAFE is not available when the CY7C455/6/7 is cascaded for depth expansion. All flags are synchronous, meaning that the change of states is relative to one of the clocks (CKR or CKW, as appropriate).[46] The Empty and Almost Empty flag states are exclusively updated by each rising edge of the read clock (CKR). For example, when the FIFO contains 1 word, the next read (rising edge of CKR while ENR=LOW) causes the flag pins to output a state that represents Empty. The Half Full, Almost Full, and Full flag states are updated exclusively by the write clock (CKW). For example, if the CY7C457 contains 2,047 words (2,048 words indicate Full for the CY7C457), the next write (rising edge of CKW while ENW=LOW) causes the flag pins to output a state that is decoded as Full. Since the flags denoting emptiness (Empty, Almost Empty) are only updated by CKR and the flags signifying fullness (Half Full, Almost Full, Full) are exclusively updated by CKW, careful attention must be given to the flag operation. The user must be aware that if a boundary (Empty, Almost Empty, Half Full, Almost Full, or Full) is crossed due to an operation from a clock that the flag is not synchronized to (i.e., CKW does not affect Empty or Almost Empty), a flag update cycle is necessary to represent the FIFO's new state. The signal to which a flag is not synchronized will be referred to as the opposite clock (CKW is opposite clock for Empty and Almost Empty flags; CKR is the opposite clock for Half Full, Almost Full, and Full flags). Until a proper flag update cycle is executed, the synchronous flags will not show the new state of the FIFO.
Programming
The CY7C455/6/7 is programmed during a master reset cycle. If MR and ENW are LOW, a rising edge on CKW will write the D0-7,8,or9 and D 15-17 inputs into the programming register [45]. MR must be set up a minimum of tSMRP before the program write rising edge and held tHMRP after the program write falling edge. The user has the ability to also perform a program read during the master reset cycle. This will occur at the rising edge of CKR when MR and ENR are asserted. The program read must be performed a minimum of t FTP after a program write, and the program word will be available tAP after the read occurs. If a program write does not occur, a program read may occur a minimum of tSMRP after MR is asserted. This will read the default program value.
Notes: 45. CKW will write D0-9 into the programming register. CKR will read D0-9 during a programming register read. 46. The synchronous architecture guarantees the flags valid for approximately one cycle of the clock they are synchronized to.
16
CY7C455 CY7C456 CY7C457
When updating flags, the FIFO must make a decision as to whether or not the opposite clock was recognized when a clock updates the flag. For example (when updating the Empty flag), if a write occurs at least tSKEW1 after a read, the write is guaranteed not to be included when CKR updates the flag. If a write occurs at least tSKEW2 before a read, the write is guaranteed to be included when CKR updates flag. If a write occurs within tSKEW1 after or tSKEW2 before CKR, then the decision of whether or not to include the write when the flag is updated by CKR is arbitrary. The update cycle for non-boundary flags (Almost Empty, Half Full, Almost Full) is different from that used to update the boundary flags (Empty, Full). Both operations are described below. Boundary Flags (Full) The Full flag is synchronized to the CKW signal (i.e., the Full flag can only be updated by a clock pulse on the CKW pin). A full FIFO that is read will be described with a Full flag until a rising edge is presented to the CKW pin. When making the transition from Full to Almost Full (or Full to Greater Than Half Full), a clock cycle on CKW is necessary to update the flags to the current state. In such a state (flags showing Full even through data has been read from the FIFO), two write cycles are required to write data into the FIFO. The first write serves only to update the flags to the Almost Full or Greater Than Half Full state, while the second write inputs the data. This first write cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number of words in the FIFO). It simply deasserts the Full flag. The flag is updated regardless of the ENW state. Therefore, the update occurs even when ENW is deasserted (HIGH), so that a valid write is not necessary to update the flags to correctly describe the FIFO. In this example, the read must occur at least tSKEW2 before the flag update cycle in order for the FIFO to guarantee that the read will be included in the count when CKW updates the flags. When a free-running clock is connected to CKW, the flag updates each cycle. Full flag operation is similar to the Empty flag operation described in Table 2. Non-Boundary Flags (Almost Empty, Half Full, Almost Full) The CY7C455/6/7 features programmable Almost Empty and Almost Full flags. Each flag can be programmed a specific distance from the corresponding boundary flags (Empty or Full). The flags can be programmed to be activated at the Empty or Full boundary, or at any distance from the Empty/Full boundary. When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAFE flag will be asserted signifying that the FIFO is Almost Empty. When the FIFO is within that same number of empty locations from being Full, the PAFE will also be asserted signifying that the FIFO is Almost Full. The HF flag is decoded to distinguish the states. The default distance from where PAFE becomes active to the boundary (Empty, Full) is 16 words/locations. The Almost Full and Almost Empty flags can be programmed so that they are only active at Full and Empty boundaries. However, the operation will remain consistent with the non-boundary flag operation that is discussed below. 7C456 Words in FIFO 0 1 => P P + 1 => 512 513 => 1023 - P 1024 - P => 1023 1024 7C457 Words in FIFO 0 1 => P P + 1 => 1024 1025 => 2047 - P 2048 - P => 2047 2048
Boundary and Non-Boundary Flags
Boundary Flags (Empty) The Empty flag is synchronized to the CKR signal (i.e., the Empty flag can only be updated by a clock pulse on the CKR pin). An empty FIFO that is written to will be described with an Empty flag state until a rising edge is presented to the CKR pin. When making the transition from Empty to Almost Empty (or Empty to Less than or Equal to Half Full), a clock cycle on CKR is necessary to update the flags to the current state. In such a state (flags showing Empty even though data has been written to the FIFO), two read clock cycles are required to read data out of the FIFO. The first read serves only to update the flags to the Almost Empty or Less than or Equal to Half Full state, while the second read outputs the data. This first read cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number of words in FIFO). It simply deasserts the Empty flag. The flag is updated regardless of the ENR state. Therefore, the update occurs even when ENR is deasserted (HIGH), so that a valid read is not necessary to update the flags to correctly describe the FIFO. In this example, the write must occur at least tSKEW2 before the flag update cycle in order for the FIFO to guarantee that the write will be included in the count when CKR updates the flags. When a free-running clock is connected to CKR, the flag is updated each cycle. Table 2 shows an example of a sequence of operations that update the Empty flag.
.
Table 1. Flag Truth Table[47] E/F 0 1 1 1 1 0 PAFE 0 0 1 1 0 0 HF 1 1 1 0 0 0 State Empty Almost Empty Less than or Equal to Half Full Greater than Half Full Almost Full Full 7C455 Words in FIFO 0 1 => P P + 1 => 256 257 => 511 - P 512 - P => 511 512
Notes: 47. P is the decimal value of the binary number represented by D0-7 for the CY7C455, D 0-8 for the CY7C456, and D 0-9 for the CY7C457. P = 0 signifies that the Almost Empty state = Empty state.
17
CY7C455 CY7C456 CY7C457
Table 2. Empty Flag (Boundary Flag) Operation Example Status Before Operation Current State of FIFO Empty Empty Empty AE AE Empty Empty AE Number of Words in FIFO 0 1 2 2 1 0 1 1 Status After Operation Next State of FIFO Empty Empty AE AE Empty Empty AE Empty Number of Words in FIFO 1 2 2 1 0 1 1 0 Write Write Flag Update Read Read (transition from Almost Empty to Empty) Write Flag Update Read (transition from Almost Empty to Empty)
E/F 0 0 0 1 1 0 1 1
AFE 0 0 0 0 0 0 0 0
HF 1 1 1 1 1 1 1 1
Operation Write (ENW = 0) Write (ENW = 0) Read (ENR = X) Read (ENR = 0) Read (ENR = 0) Write (ENR = 0) Read (ENR = X) Read (ENR = 0)
E/F 0 0 1 1 0 0 1 0
AFE 0 0 0 0 0 0 0 0
HF 1 1 1 1 1 1 1 1
Comments
Almost Empty is only updated by CKR while Half Full and Almost Full are updated by CKW. Non-boundary flags employ flag update cycles similar to the boundary flag latent cycles in order to update the FIFO status. For example, if the FIFO just reaches the Greater than Half Full state, and then two words are read from the FIFO, a write clock (CKW) will be required to update the flags to the Less than Half Full state. However, unlike the boundary flag latent cycle, the state of the enable pin (ENW in this case) affects the operation. Therefore, set-up and hold times for the enable pins must be met (tSEN and tHEN). If the enable pin is active during the flag update cycle, the count and data are updated in addition to PAFE and HF. If the enable pin is not asserted during the flag update cycle, only the flags are updated. Table 3 shows an example of a sequence of operations that update the Almost Empty and Almost Full flags The CY7C455/6/7 also features even or odd parity checking and generation. D 15-17 are used during a program write to describe the parity option desired. Table 4 summarizes programmable parity options. If the user elects not to program the device, then parity is disabled. Parity information is provided on two multi-mode output pins (Q8/PG1/PE1 and Q 17/PG2/PE2). The three possible modes are described in the following paragraphs.
ignored. The parity bits are stored internally as D 8 and D 17, and during a subsequent read will be available on the PG1 and PG2 pins along with the data words from which the parity was generated (Q 0-7 and Q 9-16). For example, if parity generate is set to ODD and the D0-7 inputs have an EVEN number of 1s, PG1 will be HIGH. Parity Check (PE mode) If the FIFO is programmed for parity checking, it will compare the parity of D 0-8 and D 9-17 with the program register. For example, D 8 and D 17 will be set according to the result of the parity check on each word. When these words are later read, PE1 and PE 2 will reflect the result of the parity check. If a parity error occurs in D 0-8, D 8 will be set LOW internally. When this word is later read, PE 1 will be LOW.
Retransmit
The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted.
Programmable Parity
Parity Disabled (Q8/Q 17 mode) When parity is disabled (or the user does not program parity option) the FIFO stores all 18 bits present on D 0-17 inputs internally and will output all 18 bits on Q0-17. Parity Generate (PG mode) This mode is used to generate either even or odd parity (as programmed) from D0-7 and D 9-16. D8 and D 17 inputs are
18
CY7C455 CY7C456 CY7C457
Width Expansion Modes
During width expansion all flags (programmable and nonprogrammable) are available. These FIFOs can be expanded in width to provide word width greater than 18 in increments of 18. During width expansion mode all control line inputs are common. When the FIFO is being read near the Empty (Full) boundary, it is important to note that both sets of flags should be checked to see if they have been updated to the Not Empty (Not Full) condition to insure that the next read (write) will perform the same operation on all devices. Checking all sets of flags is critical so that data is not read from the FIFOs "staggered" by one clock cycle. This situation could occur when the first write to an empty FIFO and a read are very close together. If the read occurs less than tSKEW2 after the first write to two width-expanded devices, A and B, device A may go Almost Empty (read recognized as flag update) while device B stays Empty (read ignored). This occurs because a read can be either recognized or ignored if it occurs within tSKEW2 of a write. The next read cycle outputs the first half of the first word on device A while device B updates its flags to Almost Empty. Subsequent reads will continue to output "staggered" data assuming more data has been written to FIFOs. next device, with XO of the last device connected to XI of the first device. The first device has its first load pin (FL) tied to V SS while all other devices must have this pin tied to V CC. The first device will be the first to be write and read enabled after a master reset. Proper operation also requires that all cascaded devices have common CKW, CKR, ENW, ENR, D 0-17, Q 0-17, and MR pins. When cascaded, one device at a time will be read enabled so as to avoid bus contention. By asserting XO when appropriate, the currently enabled FIFO alerts the next FIFO that it should be enabled. The next rising edge on CKR puts Q 0-17 outputs of the first device into a high-impedance state. This occurs regardless of the state of ENR or the next FIFO's Empty flag. Therefore, if the next FIFO is empty or undergoing a latent cycle, the Q 0-17 bus will be in a high-impedance state until the next device receives its first read, which brings its data to the Q 0-17 bus.
Program Write/Read of Cascaded Devices
Programming of cascaded FIFOs is the same as for a single device. Because the controls of the FIFOs are in parallel when cascaded, they all get programmed the same. During program mode, only parity is programmed since Almost Full and Almost Empty flags are not available when CY7C455/6/7 is cascaded. Only the "first device" (FIFO with FL=LOW) will output its program register contents on Q 0-7 during a program read. Q 0-17 of all other devices will remain in a high-impedance state to avoid bus contention.
Depth Expansion Mode
The CY7C455/6/7 can operate up to 83.3 MHz when cascaded. Depth expansion is accomplished by connecting expansion out (XO) of the first device to expansion in (XI) of the
CKW ENW
CKR ENR
XI D0 -
17
Q0 -
17
CKW CKR CY7C455,6,7 ENW ENR MR DATA IN OE D0- 17 MR HF DATA OUT E/F FL/RT PAFE/XO Q0- 17 VSS
XI D0 -
17
Q0 -
17
CKR CKW CY7C455,6,7 ENW ENR MR OE HF E/F FL/RT PAFE/XO VCC FULL EMPTY
c455-25
Figure 1. Depth Expansion with CY7C455/6/7
19
CY7C455 CY7C456 CY7C457
Table 3. Almost Empty Flag (Non-Boundary Flag) Operation Example[48] Status Before Operation Current State of FIFO E/F AE AE AE AFE 0 0 0 1 1
HF 1 1 1 1 1
Operation Write (ENW = 0) Write (ENW = 0) Read (ENR = 0) Read (ENR = 1) Read (ENR = 0)
E/F PAFE 1 1 1 1 1 0 0 1 1 0
HF 1 1 1 1 1
Comments Write Write Flag Update and Read Ignored Read (ENR = 1) Read (transition from Table 4. Programmable Parity Options D17 0 1 1 1 1 D16 X 0 0 1 1 D15 X 0 1 0 1 Parity disabled. Generate even parity on PG output pin. Generate odd parity on PG output pin. Check for even parity. Indicate error on PE output pin. Check for odd parity. Indicate error on PE output pin. Condition
Note: 48. Applies to CY7C455/6/7 operations when devices are programmed so that Almost Empty becomes active when the FIFO contains 32 or fewer words.
20
CY7C455 CY7C456 CY7C457
Ordering Information
512x18 Clocked FIFO Speed (ns) 12 Ordering Code CY7C455-12JC CY7C455-12NC CY7C455-12JI 14 CY7C455-14JC CY7C455-14NC CY7C455-14JI 20 CY7C455-20JC CY7C455-20NC CY7C455-20JI 30 CY7C455-30JC CY7C455-30NC CY7C455-30JI 1Kx18 Clocked FIFO Speed (ns) 12 Ordering Code CY7C456-12JC CY7C456-12NC CY7C456-12JI 14 CY7C456-14JC CY7C456-14NC CY7C456-14JI 20 CY7C456-20JC CY7C456-20NC CY7C456-20JI 30 CY7C456-30JC CY7C456-30NC CY7C456-30JI 2Kx18 Clocked FIFO Speed (ns) 12 Ordering Code CY7C457-12JC CY7C457-12NC CY7C457-12JI 14 CY7C457-14JC CY7C457-14NC CY7C457-14JI 20 CY7C457-20JC CY7C457-20NC CY7C457-20JI 30 CY7C457-30JC CY7C457-30NC CY7C457-30JI Document #: 38-00211-E 21 Package Name J69 N52 J69 J69 N52 J69 J69 N52 J69 J69 N52 J69 Package Type 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier Industrial Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial Package Name J69 N52 J69 J69 N52 J69 J69 N52 J69 J69 N52 J69 Package Type 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier Industrial Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial Package Name J69 N52 J69 J69 N52 J69 J69 N52 J69 J69 N52 J69 Package Type 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier Industrial Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial
CY7C455 CY7C456 CY7C457
Package Diagrams
52-Lead Plastic Leaded Chip Carrier J69
52-Lead Plastic Quad Flatpack N52
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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